ref: cd3850c1d97d3a21e53e79c0a7feb6f052feb181
parent: 7cb545370bcda90b8a6cc65347b42ef362cea1f9
author: Timothy B. Terriberry <[email protected]>
date: Wed May 22 11:11:59 EDT 2013
Port 1ed17cc2 to C_MUL and C_MUL4. Measures a 0.1% speedup on 96 kbps stereo encode+decode on a Cortex A8.
--- a/celt/arm/kiss_fft_armv4.h
+++ b/celt/arm/kiss_fft_armv4.h
@@ -40,18 +40,18 @@
int tt__; \
__asm__ __volatile__( \
"#C_MUL\n\t" \
- "ldm %[ap], {r0,r1}\n\t" \"ldrsh %[br], [%[bp], #0]\n\t" \
+ "ldm %[ap], {r0,r1}\n\t" \"ldrsh %[bi], [%[bp], #2]\n\t" \
"smull %[tt], %[mi], r1, %[br]\n\t" \
"smlal %[tt], %[mi], r0, %[bi]\n\t" \
"rsb %[bi], %[bi], #0\n\t" \
- "smull r0, %[mr], %[br], r0\n\t" \
+ "smull %[br], %[mr], r0, %[br]\n\t" \
"mov %[tt], %[tt], lsr #15\n\t" \
- "smlal r0, %[mr], r1, %[bi]\n\t" \
+ "smlal %[br], %[mr], r1, %[bi]\n\t" \
"orr %[mi], %[tt], %[mi], lsl #17\n\t" \
- "mov r0, r0, lsr #15\n\t" \
- "orr %[mr], r0, %[mr], lsl #17\n\t" \
+ "mov %[br], %[br], lsr #15\n\t" \
+ "orr %[mr], %[br], %[mr], lsl #17\n\t" \
: [mr]"=r"((m).r), [mi]"=r"((m).i), \
[br]"=&r"(br__), [bi]"=r"(bi__), [tt]"=r"(tt__) \
: [ap]"r"(&(a)), [bp]"r"(&(b)) \
@@ -68,18 +68,18 @@
int tt__; \
__asm__ __volatile__( \
"#C_MUL4\n\t" \
- "ldm %[ap], {r0,r1}\n\t" \"ldrsh %[br], [%[bp], #0]\n\t" \
+ "ldm %[ap], {r0,r1}\n\t" \"ldrsh %[bi], [%[bp], #2]\n\t" \
"smull %[tt], %[mi], r1, %[br]\n\t" \
"smlal %[tt], %[mi], r0, %[bi]\n\t" \
"rsb %[bi], %[bi], #0\n\t" \
- "smull r0, %[mr], %[br], r0\n\t" \
+ "smull %[br], %[mr], r0, %[br]\n\t" \
"mov %[tt], %[tt], lsr #17\n\t" \
- "smlal r0, %[mr], r1, %[bi]\n\t" \
+ "smlal %[br], %[mr], r1, %[bi]\n\t" \
"orr %[mi], %[tt], %[mi], lsl #15\n\t" \
- "mov r0, r0, lsr #17\n\t" \
- "orr %[mr], r0, %[mr], lsl #15\n\t" \
+ "mov %[br], %[br], lsr #17\n\t" \
+ "orr %[mr], %[br], %[mr], lsl #15\n\t" \
: [mr]"=r"((m).r), [mi]"=r"((m).i), \
[br]"=&r"(br__), [bi]"=r"(bi__), [tt]"=r"(tt__) \
: [ap]"r"(&(a)), [bp]"r"(&(b)) \