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Adding decoder state validation

--- a/celt/celt.h

+++ b/celt/celt.h

@@ -209,6 +209,13 @@

 extern const signed char tf_select_table[4][8];

+#if defined(ENABLE_HARDENING) || defined(ENABLE_ASSERTIONS)

+void validate_celt_decoder(CELTDecoder *st);

+#define VALIDATE_CELT_DECODER(st) validate_celt_decoder(st)

+#else

+#define VALIDATE_CELT_DECODER(st)

+#endif

+

 int resampling_factor(opus_int32 rate);

 void celt_preemphasis(const opus_val16 * OPUS_RESTRICT pcmp, celt_sig * OPUS_RESTRICT inp,

--- a/celt/celt_decoder.c

+++ b/celt/celt_decoder.c

@@ -51,6 +51,14 @@

 #include "celt_lpc.h"

 #include "vq.h"

+/* The maximum pitch lag to allow in the pitch-based PLC. It's possible to save

+   CPU time in the PLC pitch search by making this smaller than MAX_PERIOD. The

+   current value corresponds to a pitch of 66.67 Hz. */

+#define PLC_PITCH_LAG_MAX (720)

+/* The minimum pitch lag to allow in the pitch-based PLC. This corresponds to a

+   pitch of 480 Hz. */

+#define PLC_PITCH_LAG_MIN (100)

+

 #if defined(SMALL_FOOTPRINT) && defined(FIXED_POINT)

 #define NORM_ALIASING_HACK

 #endif

@@ -101,6 +109,38 @@

    /* opus_val16 backgroundLogE[], Size = 2*mode->nbEBands */

 };

+#if defined(ENABLE_HARDENING) || defined(ENABLE_ASSERTIONS)

+/* Make basic checks on the CELT state to ensure we don't end

+   up writing all over memory. */

+void validate_celt_decoder(CELTDecoder *st)

+{

+#ifndef CUSTOM_MODES

+   celt_assert(st->mode == opus_custom_mode_create(48000, 960, NULL));

+   celt_assert(st->overlap == 120);

+#endif

+   celt_assert(st->channels == 1 || st->channels == 2);

+   celt_assert(st->stream_channels == 1 || st->stream_channels == 2);

+   celt_assert(st->downsample > 0);

+   celt_assert(st->start == 0 || st->start == 17);

+   celt_assert(st->start < st->end);

+   celt_assert(st->end <= 21);

+#ifdef OPUS_ARCHMASK

+   celt_assert(st->arch >= 0);

+   celt_assert(st->arch <= OPUS_ARCHMASK);

+#endif

+   celt_assert(st->last_pitch_index <= PLC_PITCH_LAG_MAX);

+   celt_assert(st->last_pitch_index >= PLC_PITCH_LAG_MIN || st->last_pitch_index == 0);

+   celt_assert(st->postfilter_period < MAX_PERIOD);

+   celt_assert(st->postfilter_period >= COMBFILTER_MINPERIOD || st->postfilter_period == 0);

+   celt_assert(st->postfilter_period_old < MAX_PERIOD);

+   celt_assert(st->postfilter_period_old >= COMBFILTER_MINPERIOD || st->postfilter_period_old == 0);

+   celt_assert(st->postfilter_tapset <= 2);

+   celt_assert(st->postfilter_tapset >= 0);

+   celt_assert(st->postfilter_tapset_old <= 2);

+   celt_assert(st->postfilter_tapset_old >= 0);

+}

+#endif

+

 int celt_decoder_get_size(int channels)

 {

    const CELTMode *mode = opus_custom_mode_create(48000, 960, NULL);

@@ -437,14 +477,6 @@

    }

 }

-/* The maximum pitch lag to allow in the pitch-based PLC. It's possible to save

-   CPU time in the PLC pitch search by making this smaller than MAX_PERIOD. The

-   current value corresponds to a pitch of 66.67 Hz. */

-#define PLC_PITCH_LAG_MAX (720)

-/* The minimum pitch lag to allow in the pitch-based PLC. This corresponds to a

-   pitch of 480 Hz. */

-#define PLC_PITCH_LAG_MIN (100)

-

 static int celt_plc_pitch_search(celt_sig *decode_mem[2], int C, int arch)

 {

    int pitch_index;

@@ -832,6 +864,7 @@

    const opus_int16 *eBands;

    ALLOC_STACK;

+   VALIDATE_CELT_DECODER(st);

    mode = st->mode;

    nbEBands = mode->nbEBands;

    overlap = mode->overlap;