ref: 9f6970511aa381ee085c0f6797a4acd280a9464f
parent: f97e207c661b21747119784d7dea76fb91f6d13f
author: Ori Bernstein <[email protected]>
date: Wed Dec 18 18:16:55 EST 2013
Add fix for byte multiplies. Imul has a two register form for all types but 8 bytes. This is dumb. So, we need to special case byte multiplies.
--- a/6/insns.def
+++ b/6/insns.def
@@ -32,6 +32,7 @@
Insn(Iadd, "\tadd%t %x,%r\n", Use(.l={1,2}), Def(.l={2}))
Insn(Isub, "\tsub%t %x,%r\n", Use(.l={1,2}), Def(.l={2}))
Insn(Iimul, "\timul%t %x,%r\n", Use(.l={1,2}), Def(.l={2}))
+Insn(Iimul_r, "\timul%t %r\n", Use(.l={1},.r={Ral}), Def(.r={Rax}))
Insn(Imul, "\tmul%t %r\n", Use(.l={1},.r={Reax}), Def(.r={Reax,Redx}))
Insn(Idiv, "\tdiv%t %r\n", Use(.l={1},.r={Reax,Redx}), Def(.r={Reax,Redx}))
Insn(Ineg, "\tneg%t %r\n", Use(.l={1}), Def(.l={1}))
--- a/6/isel.c
+++ b/6/isel.c
@@ -461,8 +461,18 @@
case Omul:
if (floattype(exprtype(n)))
r = binop(s, Ifmul, args[0], args[1]);
- else
+ else if (size(args[0]) == 1) {
+ a = selexpr(s, args[0]);
+ b = selexpr(s, args[1]);
+
+ c = locphysreg(Ral);
+ r = locreg(a->mode);
+ g(s, Imov, a, c, NULL);
+ g(s, Iimul_r, b, NULL);
+ g(s, Imov, c, r, NULL);
+ } else {
r = binop(s, Iimul, args[0], args[1]);
+ }
break;
case Odiv:
case Omod:
--- a/test/tests
+++ b/test/tests
@@ -22,6 +22,7 @@
B splitline E 3
B add E 53
B mul E 42
+B mul8 E 18
B div E 42
B mod E 6
B bsr E 5