ref: 814f0d3958f7ac453d2913363a87238cc5c03a5f
parent: 79dbe0f5f75ea9da8f5b33b2c96842223ade42c7
author: Ori Bernstein <[email protected]>
date: Sun Jul 15 23:07:52 EDT 2012
Be pickier about instruction formats.
We used to pass them all through with no effort to verify them.
Don't do that.
--- a/8/asm.h
+++ b/8/asm.h
@@ -179,7 +179,7 @@
Loc *locmemls(char *disp, Loc *base, Loc *idx, int scale, Mode mode);
Loc *loclit(long val);
-void locprint(FILE *fd, Loc *l);
+void locprint(FILE *fd, Loc *l, char spec);
void iprintf(FILE *fd, Insn *insn);
/* register allocation */
--- a/8/insns.def
+++ b/8/insns.def
@@ -2,14 +2,15 @@
is defined by the following macro:
Insn(enumval, fmt, attr)
The format string 'fmt' has the following expansions:
- %r - A register
- %m - A memory location.
- %l - A location (either register or memory)
- %x - Any value.
+ %r - reg
+ %m - mem
+ %i - imm
+ %v - reg/mem
+ %u - reg/imm
+ %x - reg/mem/imm
%[1-9]*t - Mode of an operand. The optional number
preceeding it is the operand desired for
the mode.
- %v - a value (ie, immediate integer or label)
Currently, there aren't any attrs, because none were needed yet.
Eventually, they'll probably include flag setting and so on.
@@ -17,34 +18,34 @@
instead of 0-based. (0 is the sentinel value).
*/
-/* Note, the mov instruction is specified in an overly general manner. */
Insn(Inone, "BAD_INSN", Use(), Def())
+/* Note, the mov instruction is specified in an overly general manner. */
Insn(Imov, "\tmov%t %x,%x\n", Use(.l={1}), Def(.l={2})) Insn(Imovz, "\tmovz%1t%2t %x,%x\n", Use(.l={1}), Def(.l={2})) Insn(Imovs, "\tmovs%1t%2t %x,%x\n", Use(.l={1}), Def(.l={2}))-Insn(Ilea, "\tlea%t %x,%x\n", Use(.l={1}), Def(.l={2}))+Insn(Ilea, "\tlea%t %m,%r\n", Use(.l={1}), Def(.l={2}))-Insn(Iadd, "\tadd%t %r,%x\n", Use(.l={1,2}), Def(.l={2}))-Insn(Isub, "\tsub%t %r,%x\n", Use(.l={1,2}), Def(.l={2}))+Insn(Iadd, "\tadd%t %x,%r\n", Use(.l={1,2}), Def(.l={2}))+Insn(Isub, "\tsub%t %x,%r\n", Use(.l={1,2}), Def(.l={2})) Insn(Imul, "\tmul%t %r\n", Use(.l={1},.r={Reax}), Def(.r={Reax,Redx})) Insn(Idiv, "\tdiv%t %r\n", Use(.l={1},.r={Reax,Redx}), Def(.r={Reax,Redx})) Insn(Ineg, "\tneg%t %r\n", Use(.l={1}), Def(.l={1}))-Insn(Iand, "\tand%t %r,%x\n", Use(.l={1,2}), Def(.l={2}))-Insn(Ior, "\tor%t %r,%x\n", Use(.l={1,2}), Def(.l={2}))-Insn(Ixor, "\txor%t %r,%x\n", Use(.l={1,2}), Def(.l={2}))-Insn(Inot, "\tnot%t %x\n", Use(.l={1}), Def(.l={1}))-Insn(Ishl, "\tsal%2t %r,%x\n", Use(.l={1,2}), Def(.l={2}))-Insn(Isar, "\tshr%2t %r,%x\n", Use(.l={1,2}), Def(.l={2}))-Insn(Ishr, "\tshr%2t %r,%x\n", Use(.l={1,2}), Def(.l={2}))+Insn(Iand, "\tand%t %x,%r\n", Use(.l={1,2}), Def(.l={2}))+Insn(Ior, "\tor%t %x,%r\n", Use(.l={1,2}), Def(.l={2}))+Insn(Ixor, "\txor%t %x,%r\n", Use(.l={1,2}), Def(.l={2}))+Insn(Inot, "\tnot%t %v\n", Use(.l={1}), Def(.l={1}))+Insn(Ishl, "\tsal%2t %u,%r\n", Use(.l={1,2}), Def(.l={2}))+Insn(Isar, "\tshr%2t %u,%r\n", Use(.l={1,2}), Def(.l={2}))+Insn(Ishr, "\tshr%2t %u,%r\n", Use(.l={1,2}), Def(.l={2}))-Insn(Itest, "\ttest%t %r,%r\n", Use(.l={1,2}), Def(.l={2}))-Insn(Icmp, "\tcmp%t %r,%r\n", Use(.l={1,2}), Def(.l={2}))+Insn(Itest, "\ttest%t %u,%r\n", Use(.l={1,2}), Def(.l={2}))+Insn(Icmp, "\tcmp%t %u,%r\n", Use(.l={1,2}), Def(.l={2})) Insn(Ipush, "\tpush%t %r\n", Use(.l={1}), Def()) Insn(Ipop, "\tpop%t %r\n", Use(.l={1}), Def())/* branch instructions */
-Insn(Isetz, "\tsetz %v\n", Use(), Def(.l={1}))+Insn(Isetz, "\tsetz %v\n", Use(), Def(.l={1})) Insn(Isetnz, "\tsetnz %v\n", Use(), Def(.l={1})) Insn(Isetlt, "\tsetlt %v\n", Use(), Def(.l={1})) Insn(Isetle, "\tsetle %v\n", Use(), Def(.l={1}))--- a/8/isel.c
+++ b/8/isel.c
@@ -570,14 +570,14 @@
return r;
}
-void locprint(FILE *fd, Loc *l)
+void locprint(FILE *fd, Loc *l, char spec)
{-
switch (l->type) {case Loclbl:
fprintf(fd, "%s", l->lbl);
break;
case Locreg:
+ assert(spec == 'r' || spec == 'v' || spec == 'x' || spec == 'u');
if (l->reg.colour == Rnone)
fprintf(fd, "%%P.%ld", l->reg.id);
else
@@ -585,6 +585,7 @@
break;
case Locmem:
case Locmeml:
+ assert(spec == 'm' || spec == 'v' || spec == 'x');
if (l->type == Locmem) {if (l->mem.constdisp)
fprintf(fd, "%ld", l->mem.constdisp);
@@ -593,10 +594,10 @@
fprintf(fd, "%s", l->mem.lbldisp);
}
fprintf(fd, "(");- locprint(fd, l->mem.base);
+ locprint(fd, l->mem.base, 'r');
if (l->mem.idx) {fprintf(fd, ",");
- locprint(fd, l->mem.idx);
+ locprint(fd, l->mem.idx, 'r');
}
if (l->mem.scale > 1)
fprintf(fd, ",%d", l->mem.scale);
@@ -604,6 +605,7 @@
fprintf(fd, ")");
break;
case Loclit:
+ assert(spec == 'i' || spec == 'x' || spec == 'u');
fprintf(fd, "$%ld", l->lit);
break;
case Locnone:
@@ -632,12 +634,13 @@
switch (*p) {case '\0':
goto done; /* skip the final p++ */
- case 'r':
- case 'm':
- case 'l':
- case 'x':
- case 'v':
- locprint(fd, insn->args[i]);
+ case 'r': /* register */
+ case 'm': /* memory */
+ case 'i': /* imm */
+ case 'v': /* reg/mem */
+ case 'u': /* reg/imm */
+ case 'x': /* reg/mem/imm */
+ locprint(fd, insn->args[i], *p);
i++;
break;
case 't':
--- a/8/ra.c
+++ b/8/ra.c
@@ -533,9 +533,9 @@
if (debugopt['r']) { printf("Combine ");- locprint(stdout, locmap[u]);
+ locprint(stdout, locmap[u], 'x');
printf(" ==> ");- locprint(stdout, locmap[v]);
+ locprint(stdout, locmap[v], 'x');
printf("\n");}
if (wlhas(s->wlfreeze, s->nwlfreeze, v, &idx))
@@ -698,7 +698,7 @@
for (i = 0; i < K; i++) { if (!taken[i]) { if (debugopt['r']) {- locprint(stdout, n);
+ locprint(stdout, n, 'x');
printf(" ==> %s\n", regnames[regmap[i][n->mode]]);}
n->reg.colour = regmap[i][n->mode];
@@ -780,7 +780,7 @@
for (i = 0; i < bsmax(s); i++) { if (bshas(s, i)) {fprintf(fd, "%s", sep);
- locprint(fd, locmap[i]);
+ locprint(fd, locmap[i], 'x');
sep = ",";
}
}
@@ -797,9 +797,9 @@
for (i = 0; i < maxregid; i++) { for (j = i; j < maxregid; j++) { if (gbhasedge(s, i, j)) {- locprint(fd, locmap[i]);
+ locprint(fd, locmap[i], 'x');
fprintf(fd, " -- ");
- locprint(fd, locmap[j]);
+ locprint(fd, locmap[j], 'x');
fprintf(fd, "\n");
}
}