ref: 442bdf2e2cdde057cd3199f67296ef58d5bacb79
parent: 1a2e9ac076148c21d82d3ad6f730af3d7f88692a
author: mia soweli <[email protected]>
date: Thu Aug 31 12:37:33 EDT 2023
9: remove n900 naming from files that do not require it this is preparation for eventually bringing this into the upstream 9front omap kernel.
--- a/sys/src/9/n900/devkbd.c
+++ /dev/null
@@ -1,243 +1,0 @@
-#include "u.h"
-#include "../port/lib.h"
-#include "../port/error.h"
-#include "mem.h"
-#include "dat.h"
-#include "fns.h"
-#include "io.h"
-#include "../port/i2c.h"
-
-enum {- Rctrl = 0xd2,
- Csoftreset = 1<<0,
- Csoftmode = 1<<1,
- Cenable = 1<<6,
- Rcode = 0xdb,
- Risr = 0xe3,
- Rimr = 0xe4,
- Ikp = 1<<0,
- Ilk = 1<<1,
- Ito = 1<<2,
- Rsir = 0xe7,
- Redr = 0xe8,
- Ekpfalling = 1<<0,
- Ekprising = 1<<1,
- Elkfalling = 1<<2,
- Elkrising = 1<<3,
- Etofalling = 1<<4,
- Etorising = 1<<5,
- Emisfalling = 1<<6,
- Emisrising = 1<<7,
- Rsih = 0xe9,
- Scor = 1<<2,
-};
-
-enum {- Qdir,
- Qscan,
-};
-
-typedef struct Ctlr Ctlr;
-struct Ctlr {- Ref;
- Lock;
-
- I2Cdev *dev;
- Queue *q;
-
- uchar cur[8];
- uchar prev[8];
-};
-
-static Ctlr ctlr;
-static Dirtab kbdtab[] = {- ".", {Qdir, 0, QTDIR}, 0, 0555,- "scancode", {Qscan, 0, QTFILE}, 0, 0440,-};
-
-static u8int
-csr8r(Ctlr *ctlr, u8int r)
-{- uchar buf;
-
- i2crecv(ctlr->dev, &buf, sizeof(buf), r);
- return buf;
-}
-
-static u8int
-csr8w(Ctlr *ctlr, u8int r, u8int w)
-{- i2csend(ctlr->dev, &w, sizeof(w), r);
- return w;
-}
-
-static void
-kbdinterrupt(Ureg *, void*)
-{- int i, j, c, k;
-
- ilock(&ctlr);
- if(!(csr8r(&ctlr, Risr) & Ikp)) {- iunlock(&ctlr);
- return;
- }
-
- /* scan key columns */
- for(i = 0; i < 8; i++) {- ctlr.prev[i] = ctlr.cur[i];
- ctlr.cur[i] = csr8r(&ctlr, Rcode + i);
-
- /* changed? */
- c = ctlr.cur[i] ^ ctlr.prev[i];
- if(!c)
- continue;
-
- /* scan key rows */
- for(j = 0; j < 8; j++) {- if(!(c & (1 << j)))
- continue;
-
- /* pressed or released? */
- k = i << 3 | j;
- if(ctlr.prev[i] & (1 << j))
- k |= 0x80;
-
- qproduce(ctlr.q, &k, 1);
- }
- }
-
- iunlock(&ctlr);
-}
-
-static void
-kbdreset(void)
-{- ilock(&ctlr);
- ctlr.q = qopen(1024, Qcoalesce, 0, 0);
- if(!ctlr.q) {- iunlock(&ctlr);
- return;
- }
-
- ctlr.dev = i2cdev(i2cbus("i2c1"), 0x4a);- if(!ctlr.dev) {- iunlock(&ctlr);
- return;
- }
-
- ctlr.dev->subaddr = 1;
- ctlr.dev->size = 0x100;
-
- csr8w(&ctlr, Rctrl, Csoftreset | Csoftmode | Cenable);
- csr8w(&ctlr, Rsih, Scor);
- csr8w(&ctlr, Rimr, ~Ikp);
-
- intrenable(IRQTWL, kbdinterrupt, nil, BUSUNKNOWN, "kbd");
- iunlock(&ctlr);
-}
-
-static void
-kbdshutdown(void)
-{-}
-
-static Chan *
-kbdattach(char *spec)
-{- if(!ctlr.dev)
- error(Enonexist);
-
- return devattach(L'b', spec);
-}
-
-static Walkqid *
-kbdwalk(Chan *c, Chan *nc, char **name, int nname)
-{- return devwalk(c, nc, name, nname, kbdtab, nelem(kbdtab), devgen);
-}
-
-static int
-kbdstat(Chan *c, uchar *dp, int n)
-{- return devstat(c, dp, n, kbdtab, nelem(kbdtab), devgen);
-}
-
-static Chan *
-kbdopen(Chan *c, int mode)
-{- if(!iseve)
- error(Eperm);
-
- if(c->qid.path == Qscan) {- if(waserror()) {- decref(&ctlr);
- nexterror();
- }
-
- if(incref(&ctlr) != 1)
- error(Einuse);
-
- c = devopen(c, mode, kbdtab, nelem(kbdtab), devgen);
- poperror();
- return c;
- }
-
- return devopen(c, mode, kbdtab, nelem(kbdtab), devgen);
-}
-
-static void
-kbdclose(Chan *c)
-{- if((c->flag & COPEN) && c->qid.path == Qscan)
- decref(&ctlr);
-}
-
-static Block*
-kbdbread(Chan *c, long n, ulong off)
-{- if(c->qid.path == Qscan)
- return qbread(ctlr.q, n);
-
- return devbread(c, n, off);
-}
-
-static long
-kbdread(Chan *c, void *a, long n, vlong)
-{- if(c->qid.path == Qscan)
- return qread(ctlr.q, a, n);
-
- if(c->qid.path == Qdir)
- return devdirread(c, a, n, kbdtab, nelem(kbdtab), devgen);
-
- error(Egreg);
- return 0;
-}
-
-static long
-kbdwrite(Chan *, void *, long, vlong)
-{- error(Egreg);
- return 0;
-}
-
-Dev kbddevtab = {- L'b',
- "kbd",
-
- kbdreset,
- devinit,
- kbdshutdown,
- kbdattach,
- kbdwalk,
- kbdstat,
- kbdopen,
- devcreate,
- kbdclose,
- kbdread,
- kbdbread,
- kbdwrite,
- devbwrite,
- devremove,
- devwstat,
-};
--- /dev/null
+++ b/sys/src/9/n900/devkbdtwl.c
@@ -1,0 +1,243 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "../port/error.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+#include "../port/i2c.h"
+
+enum {+ Rctrl = 0xd2,
+ Csoftreset = 1<<0,
+ Csoftmode = 1<<1,
+ Cenable = 1<<6,
+ Rcode = 0xdb,
+ Risr = 0xe3,
+ Rimr = 0xe4,
+ Ikp = 1<<0,
+ Ilk = 1<<1,
+ Ito = 1<<2,
+ Rsir = 0xe7,
+ Redr = 0xe8,
+ Ekpfalling = 1<<0,
+ Ekprising = 1<<1,
+ Elkfalling = 1<<2,
+ Elkrising = 1<<3,
+ Etofalling = 1<<4,
+ Etorising = 1<<5,
+ Emisfalling = 1<<6,
+ Emisrising = 1<<7,
+ Rsih = 0xe9,
+ Scor = 1<<2,
+};
+
+enum {+ Qdir,
+ Qscan,
+};
+
+typedef struct Ctlr Ctlr;
+struct Ctlr {+ Ref;
+ Lock;
+
+ I2Cdev *dev;
+ Queue *q;
+
+ uchar cur[8];
+ uchar prev[8];
+};
+
+static Ctlr ctlr;
+static Dirtab kbdtab[] = {+ ".", {Qdir, 0, QTDIR}, 0, 0555,+ "scancode", {Qscan, 0, QTFILE}, 0, 0440,+};
+
+static u8int
+csr8r(Ctlr *ctlr, u8int r)
+{+ uchar buf;
+
+ i2crecv(ctlr->dev, &buf, sizeof(buf), r);
+ return buf;
+}
+
+static u8int
+csr8w(Ctlr *ctlr, u8int r, u8int w)
+{+ i2csend(ctlr->dev, &w, sizeof(w), r);
+ return w;
+}
+
+static void
+kbdinterrupt(Ureg *, void*)
+{+ int i, j, c, k;
+
+ ilock(&ctlr);
+ if(!(csr8r(&ctlr, Risr) & Ikp)) {+ iunlock(&ctlr);
+ return;
+ }
+
+ /* scan key columns */
+ for(i = 0; i < 8; i++) {+ ctlr.prev[i] = ctlr.cur[i];
+ ctlr.cur[i] = csr8r(&ctlr, Rcode + i);
+
+ /* changed? */
+ c = ctlr.cur[i] ^ ctlr.prev[i];
+ if(!c)
+ continue;
+
+ /* scan key rows */
+ for(j = 0; j < 8; j++) {+ if(!(c & (1 << j)))
+ continue;
+
+ /* pressed or released? */
+ k = i << 3 | j;
+ if(ctlr.prev[i] & (1 << j))
+ k |= 0x80;
+
+ qproduce(ctlr.q, &k, 1);
+ }
+ }
+
+ iunlock(&ctlr);
+}
+
+static void
+kbdreset(void)
+{+ ilock(&ctlr);
+ ctlr.q = qopen(1024, Qcoalesce, 0, 0);
+ if(!ctlr.q) {+ iunlock(&ctlr);
+ return;
+ }
+
+ ctlr.dev = i2cdev(i2cbus("i2c1"), 0x4a);+ if(!ctlr.dev) {+ iunlock(&ctlr);
+ return;
+ }
+
+ ctlr.dev->subaddr = 1;
+ ctlr.dev->size = 0x100;
+
+ csr8w(&ctlr, Rctrl, Csoftreset | Csoftmode | Cenable);
+ csr8w(&ctlr, Rsih, Scor);
+ csr8w(&ctlr, Rimr, ~Ikp);
+
+ intrenable(IRQTWL, kbdinterrupt, nil, BUSUNKNOWN, "kbd");
+ iunlock(&ctlr);
+}
+
+static void
+kbdshutdown(void)
+{+}
+
+static Chan *
+kbdattach(char *spec)
+{+ if(!ctlr.dev)
+ error(Enonexist);
+
+ return devattach(L'b', spec);
+}
+
+static Walkqid *
+kbdwalk(Chan *c, Chan *nc, char **name, int nname)
+{+ return devwalk(c, nc, name, nname, kbdtab, nelem(kbdtab), devgen);
+}
+
+static int
+kbdstat(Chan *c, uchar *dp, int n)
+{+ return devstat(c, dp, n, kbdtab, nelem(kbdtab), devgen);
+}
+
+static Chan *
+kbdopen(Chan *c, int mode)
+{+ if(!iseve)
+ error(Eperm);
+
+ if(c->qid.path == Qscan) {+ if(waserror()) {+ decref(&ctlr);
+ nexterror();
+ }
+
+ if(incref(&ctlr) != 1)
+ error(Einuse);
+
+ c = devopen(c, mode, kbdtab, nelem(kbdtab), devgen);
+ poperror();
+ return c;
+ }
+
+ return devopen(c, mode, kbdtab, nelem(kbdtab), devgen);
+}
+
+static void
+kbdclose(Chan *c)
+{+ if((c->flag & COPEN) && c->qid.path == Qscan)
+ decref(&ctlr);
+}
+
+static Block*
+kbdbread(Chan *c, long n, ulong off)
+{+ if(c->qid.path == Qscan)
+ return qbread(ctlr.q, n);
+
+ return devbread(c, n, off);
+}
+
+static long
+kbdread(Chan *c, void *a, long n, vlong)
+{+ if(c->qid.path == Qscan)
+ return qread(ctlr.q, a, n);
+
+ if(c->qid.path == Qdir)
+ return devdirread(c, a, n, kbdtab, nelem(kbdtab), devgen);
+
+ error(Egreg);
+ return 0;
+}
+
+static long
+kbdwrite(Chan *, void *, long, vlong)
+{+ error(Egreg);
+ return 0;
+}
+
+Dev kbddevtab = {+ L'b',
+ "kbd",
+
+ kbdreset,
+ devinit,
+ kbdshutdown,
+ kbdattach,
+ kbdwalk,
+ kbdstat,
+ kbdopen,
+ devcreate,
+ kbdclose,
+ kbdread,
+ kbdbread,
+ kbdwrite,
+ devbwrite,
+ devremove,
+ devwstat,
+};
--- a/sys/src/9/n900/devrtc.c
+++ /dev/null
@@ -1,202 +1,0 @@
-#include "u.h"
-#include "../port/lib.h"
-#include "../port/error.h"
-#include "mem.h"
-#include "dat.h"
-#include "fns.h"
-#include "io.h"
-#include "../port/i2c.h"
-
-enum {- Rsec = 0x1c,
- Rmin = 0x1d,
- Rhour = 0x1e,
- Rday = 0x1f,
- Rmonth = 0x20,
- Ryear = 0x21,
- Rweeks = 0x22,
- Rctrl = 0x29,
- Cget = 1<<6,
-
- Qdir = 0,
- Qrtc,
-
- SecMin = 60,
- SecHour = 60*SecMin,
- SecDay = 24*SecHour,
-};
-
-typedef struct Ctlr Ctlr;
-struct Ctlr {- I2Cdev *dev;
-
- int sec;
- int min;
- int hour;
- int day;
- int month;
- int year;
-};
-
-static Ctlr ctlr;
-static int dmsize[] = { 365, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };-static int ldmsize[] = { 366, 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };-static Dirtab rtctab[] = {- ".", {Qdir, 0, QTDIR}, 0, 0555,- "rtc", {Qrtc, 0, QTFILE}, 0, 0440,-};
-
-#define bcddec(x) (((x) & 0xf) + ((x) >> 4) * 10)
-#define bcdenc(x) (((x / 10) << 4) + (x) % 10)
-#define leap(x) (((x) % 4) == 0 && ((x % 100) != 0 || (x % 400) == 0))
-
-static u8int
-csr8r(Ctlr *ctlr, u8int r)
-{- uchar buf;
-
- i2crecv(ctlr->dev, &buf, sizeof(buf), r);
- return buf;
-}
-
-static u8int
-csr8w(Ctlr *ctlr, u8int r, u8int w)
-{- i2csend(ctlr->dev, &w, sizeof(w), r);
- return w;
-}
-
-static vlong
-rtcsnarf(void)
-{- vlong s;
- int i;
-
- /* latch and snarf */
- csr8w(&ctlr, Rctrl, csr8r(&ctlr, Rctrl) | Cget);
- ctlr.sec = bcddec(csr8r(&ctlr, Rsec)) % 60;
- ctlr.min = bcddec(csr8r(&ctlr, Rmin)) % 60;
- ctlr.hour = bcddec(csr8r(&ctlr, Rhour)) % 24;
- ctlr.day = bcddec(csr8r(&ctlr, Rday));
- ctlr.month = bcddec(csr8r(&ctlr, Rmonth));
- ctlr.year = bcddec(csr8r(&ctlr, Ryear)) % 100;
- ctlr.year += 2000;
-
- /* seconds per year */
- s = 0;
- for(i = 1970; i < ctlr.year; i++) {- if(leap(i))
- s += ldmsize[0] * SecDay;
- else
- s += dmsize[0] * SecDay;
- }
-
- /* seconds per month */
- for(i = 1; i < ctlr.month; i++) {- if(leap(ctlr.year))
- s += ldmsize[i] * SecDay;
- else
- s += dmsize[i] * SecDay;
- }
-
- /* days, hours, minutes, seconds */
- s += (ctlr.day - 1) * SecDay;
- s += ctlr.hour * SecHour;
- s += ctlr.min * SecMin;
- s += ctlr.sec;
- return s;
-}
-
-static void
-rtcreset(void)
-{- ctlr.dev = i2cdev(i2cbus("i2c1"), 0x4b);- if(!ctlr.dev)
- return;
-
- ctlr.dev->subaddr = 1;
- ctlr.dev->size = 0x100;
-}
-
-static void
-rtcshutdown(void)
-{-}
-
-static Chan *
-rtcattach(char *spec)
-{- if(!ctlr.dev)
- error(Enonexist);
-
- return devattach('r', spec);-}
-
-static Walkqid *
-rtcwalk(Chan *c, Chan *nc, char **name, int nname)
-{- return devwalk(c, nc, name, nname, rtctab, nelem(rtctab), devgen);
-}
-
-static int
-rtcstat(Chan *c, uchar *dp, int n)
-{- return devstat(c, dp, n, rtctab, nelem(rtctab), devgen);
-}
-
-static Chan *
-rtcopen(Chan *c, int mode)
-{- mode = openmode(mode);
- if(c->qid.path == Qrtc) {- if(!iseve() && mode != OREAD)
- error(Eperm);
- }
-
- return devopen(c, mode, rtctab, nelem(rtctab), devgen);
-}
-
-static void
-rtcclose(Chan *)
-{-}
-
-static long
-rtcread(Chan *c, void *a, long n, vlong off)
-{- if(c->qid.path == Qdir)
- return devdirread(c, a, n, rtctab, nelem(rtctab), devgen);
- if(c->qid.path == Qrtc)
- return readnum(off, a, n, rtcsnarf(), 12);
-
- error(Egreg);
- return 0;
-}
-
-static long
-rtcwrite(Chan *, void *, long, vlong)
-{- error(Egreg);
- return 0;
-}
-
-Dev rtcdevtab = {- 'r',
- "rtc",
-
- rtcreset,
- devinit,
- rtcshutdown,
- rtcattach,
- rtcwalk,
- rtcstat,
- rtcopen,
- devcreate,
- rtcclose,
- rtcread,
- devbread,
- rtcwrite,
- devbwrite,
- devremove,
- devwstat,
-};
--- /dev/null
+++ b/sys/src/9/n900/devrtctwl.c
@@ -1,0 +1,202 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "../port/error.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+#include "../port/i2c.h"
+
+enum {+ Rsec = 0x1c,
+ Rmin = 0x1d,
+ Rhour = 0x1e,
+ Rday = 0x1f,
+ Rmonth = 0x20,
+ Ryear = 0x21,
+ Rweeks = 0x22,
+ Rctrl = 0x29,
+ Cget = 1<<6,
+
+ Qdir = 0,
+ Qrtc,
+
+ SecMin = 60,
+ SecHour = 60*SecMin,
+ SecDay = 24*SecHour,
+};
+
+typedef struct Ctlr Ctlr;
+struct Ctlr {+ I2Cdev *dev;
+
+ int sec;
+ int min;
+ int hour;
+ int day;
+ int month;
+ int year;
+};
+
+static Ctlr ctlr;
+static int dmsize[] = { 365, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };+static int ldmsize[] = { 366, 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };+static Dirtab rtctab[] = {+ ".", {Qdir, 0, QTDIR}, 0, 0555,+ "rtc", {Qrtc, 0, QTFILE}, 0, 0440,+};
+
+#define bcddec(x) (((x) & 0xf) + ((x) >> 4) * 10)
+#define bcdenc(x) (((x / 10) << 4) + (x) % 10)
+#define leap(x) (((x) % 4) == 0 && ((x % 100) != 0 || (x % 400) == 0))
+
+static u8int
+csr8r(Ctlr *ctlr, u8int r)
+{+ uchar buf;
+
+ i2crecv(ctlr->dev, &buf, sizeof(buf), r);
+ return buf;
+}
+
+static u8int
+csr8w(Ctlr *ctlr, u8int r, u8int w)
+{+ i2csend(ctlr->dev, &w, sizeof(w), r);
+ return w;
+}
+
+static vlong
+rtcsnarf(void)
+{+ vlong s;
+ int i;
+
+ /* latch and snarf */
+ csr8w(&ctlr, Rctrl, csr8r(&ctlr, Rctrl) | Cget);
+ ctlr.sec = bcddec(csr8r(&ctlr, Rsec)) % 60;
+ ctlr.min = bcddec(csr8r(&ctlr, Rmin)) % 60;
+ ctlr.hour = bcddec(csr8r(&ctlr, Rhour)) % 24;
+ ctlr.day = bcddec(csr8r(&ctlr, Rday));
+ ctlr.month = bcddec(csr8r(&ctlr, Rmonth));
+ ctlr.year = bcddec(csr8r(&ctlr, Ryear)) % 100;
+ ctlr.year += 2000;
+
+ /* seconds per year */
+ s = 0;
+ for(i = 1970; i < ctlr.year; i++) {+ if(leap(i))
+ s += ldmsize[0] * SecDay;
+ else
+ s += dmsize[0] * SecDay;
+ }
+
+ /* seconds per month */
+ for(i = 1; i < ctlr.month; i++) {+ if(leap(ctlr.year))
+ s += ldmsize[i] * SecDay;
+ else
+ s += dmsize[i] * SecDay;
+ }
+
+ /* days, hours, minutes, seconds */
+ s += (ctlr.day - 1) * SecDay;
+ s += ctlr.hour * SecHour;
+ s += ctlr.min * SecMin;
+ s += ctlr.sec;
+ return s;
+}
+
+static void
+rtcreset(void)
+{+ ctlr.dev = i2cdev(i2cbus("i2c1"), 0x4b);+ if(!ctlr.dev)
+ return;
+
+ ctlr.dev->subaddr = 1;
+ ctlr.dev->size = 0x100;
+}
+
+static void
+rtcshutdown(void)
+{+}
+
+static Chan *
+rtcattach(char *spec)
+{+ if(!ctlr.dev)
+ error(Enonexist);
+
+ return devattach('r', spec);+}
+
+static Walkqid *
+rtcwalk(Chan *c, Chan *nc, char **name, int nname)
+{+ return devwalk(c, nc, name, nname, rtctab, nelem(rtctab), devgen);
+}
+
+static int
+rtcstat(Chan *c, uchar *dp, int n)
+{+ return devstat(c, dp, n, rtctab, nelem(rtctab), devgen);
+}
+
+static Chan *
+rtcopen(Chan *c, int mode)
+{+ mode = openmode(mode);
+ if(c->qid.path == Qrtc) {+ if(!iseve() && mode != OREAD)
+ error(Eperm);
+ }
+
+ return devopen(c, mode, rtctab, nelem(rtctab), devgen);
+}
+
+static void
+rtcclose(Chan *)
+{+}
+
+static long
+rtcread(Chan *c, void *a, long n, vlong off)
+{+ if(c->qid.path == Qdir)
+ return devdirread(c, a, n, rtctab, nelem(rtctab), devgen);
+ if(c->qid.path == Qrtc)
+ return readnum(off, a, n, rtcsnarf(), 12);
+
+ error(Egreg);
+ return 0;
+}
+
+static long
+rtcwrite(Chan *, void *, long, vlong)
+{+ error(Egreg);
+ return 0;
+}
+
+Dev rtcdevtab = {+ 'r',
+ "rtc",
+
+ rtcreset,
+ devinit,
+ rtcshutdown,
+ rtcattach,
+ rtcwalk,
+ rtcstat,
+ rtcopen,
+ devcreate,
+ rtcclose,
+ rtcread,
+ devbread,
+ rtcwrite,
+ devbwrite,
+ devremove,
+ devwstat,
+};
--- a/sys/src/9/n900/i2cn900.c
+++ /dev/null
@@ -1,224 +1,0 @@
-#include "u.h"
-#include "../port/lib.h"
-#include "mem.h"
-#include "dat.h"
-#include "fns.h"
-#include "io.h"
-#include "../port/error.h"
-#include "../port/i2c.h"
-
-enum {- Rrev = 0x00,
- Rie = 0x04,
- Ris = 0x08,
- Ial = 1 << 0, /* arbitration lost */
- Inack = 1 << 1, /* no acknowledgement */
- Iardy = 1 << 2, /* address ready */
- Irrdy = 1 << 3, /* receive ready */
- Ixrdy = 1 << 4, /* transmit ready */
- Ibb = 1 << 12, /* bus busy */
- Iall = 0xffff,
-
- Rwe = 0x0c,
- Rsyss = 0x10,
- SSreset = 1 << 0, /* reset status */
-
- Rbuf = 0x14,
- Rcnt = 0x18,
- Rdata = 0x1c,
- Rsysc = 0x20,
- SCreset = 1 << 1, /* software reset */
-
- Rcon = 0x24,
- Cstt = 1 << 0, /* start condition */
- Cstp = 1 << 1, /* stop condiction */
- Cxoa3 = 1 << 4, /* expand address */
- Cxoa2 = 1 << 5,
- Cxoa1 = 1 << 6,
- Cxoa0 = 1 << 7,
- Cxa = 1 << 8,
- Ctrx = 1 << 9, /* transmit mode */
- Cmst = 1 << 10, /* master mode */
- Cstb = 1 << 11, /* start byte */
- Cen = 1 << 15, /* enable */
-
- Raddr = 0x2c,
-};
-
-#define csr32r(c, r) ((c)->io[(r)/4])
-#define csr32w(c, r, w) ((c)->io[(r)/4] = (w))
-
-typedef struct Ctlr Ctlr;
-struct Ctlr {- u32int *io;
- ulong irq;
-
- Rendez;
-};
-
-static Ctlr ctlr[] = {- { .io = (u32int*) PHYSI2C1, .irq = IRQI2C1 },- { .io = (u32int*) PHYSI2C2, .irq = IRQI2C2 },- { .io = (u32int*) PHYSI2C3, .irq = IRQI2C3 },-};
-
-static void
-n900i2cwaitbus(Ctlr *ctlr)
-{- /* FIXME: timeout here? */
- while(csr32r(ctlr, Ris) & Ibb)
- ;
-}
-
-static int
-n900i2cwaitirq(void *arg)
-{- Ctlr *ctlr = arg; return csr32r(ctlr, Ris);
-}
-
-static uint
-n900i2cwait(Ctlr *ctlr)
-{- uint s;
-
- /* FIXME: timeout here? */
- while(!(s = csr32r(ctlr, Ris))) {- if(!up || !islo())
- continue;
-
- tsleep(ctlr, n900i2cwaitirq, ctlr, 5);
- }
-
- return s;
-}
-
-static void
-n900i2cflush(Ctlr *ctlr)
-{- while(csr32r(ctlr, Ris) & Irrdy) {- USED(csr32r(ctlr, Rdata));
- csr32w(ctlr, Ris, Irrdy);
- }
-}
-
-static void
-n900i2cintr(Ureg *, void *arg)
-{- Ctlr *ctlr;
-
- ctlr = arg;
- wakeup(ctlr);
-}
-
-static int
-n900i2cinit(I2Cbus *bus)
-{- Ctlr *ctlr;
-
- /* reset the ctlr */
- ctlr = bus->ctlr;
- csr32w(ctlr, Rsysc, SCreset);
- csr32w(ctlr, Rcon, Cen);
-
- /* FIXME: timeout here? */
- while(!(csr32r(ctlr, Rsyss) & SSreset))
- ;
-
- intrenable(ctlr->irq, n900i2cintr, ctlr, 0, bus->name);
- return 0;
-}
-
-static int
-n900i2cio(I2Cbus *bus, uchar *pkt, int olen, int ilen)
-{- Ctlr *ctlr;
- uint con, addr, stat;
- uint o;
-
- ctlr = bus->ctlr;
- if(olen <= 0 || pkt == nil)
- return -1;
-
- o = 0;
- con = Cen | Cmst | Ctrx | Cstp | Cstt;
- if((pkt[o] & 0xf8) == 0xf0) {- /* 10-bit address: qemu has bugs, nothing on the n900 needs them.
- * con |= Cxa;
- * addr = ((pkt[o++] & 6) << 7) | pkt[o++];
- */
- return -1;
- } else {- /* 7-bit address */
- addr = pkt[o++] >> 1;
- }
-
- /* wait for bus */
- n900i2cwaitbus(ctlr);
-
- /* first attempt to probe, will get nack here if no dev */
- csr32w(ctlr, Rcnt, olen);
- csr32w(ctlr, Raddr, addr);
- csr32w(ctlr, Rcon, con);
- stat = n900i2cwait(ctlr);
- if(stat & Inack || stat & Ial) {- o = -1; goto err;
- }
-
- /* transmit */
- while(o < olen) {- stat = n900i2cwait(ctlr);
- if(stat == 0 || stat & Inack || stat & Ial) {- o = -1; goto err;
- }
-
- if(stat & Iardy) {- csr32w(ctlr, Ris, Iardy);
- break;
- }
-
- if(stat & Ixrdy) {- csr32w(ctlr, Rdata, pkt[o++]);
- csr32w(ctlr, Ris, Ixrdy);
- }
- }
-
- /* receive */
- csr32w(ctlr, Rcnt, ilen);
- csr32w(ctlr, Raddr, addr);
- csr32w(ctlr, Rcon, Cen | Cmst | Cstp | Cstt);
- while(o < olen + ilen) {- stat = n900i2cwait(ctlr);
- if(stat == 0 || stat & Inack || stat & Ial) {- o = -1; goto err;
- }
-
- if(stat & Iardy) {- csr32w(ctlr, Ris, Iardy);
- break;
- }
-
- if(stat & Irrdy) {- pkt[o++] = csr32r(ctlr, Rdata);
- csr32w(ctlr, Ris, Irrdy);
- }
- }
-
-err:
- n900i2cflush(ctlr);
- csr32w(ctlr, Ris, Iall);
- return o;
-}
-
-void
-i2cn900link(void)
-{- int i;
- static I2Cbus bus[] = {- { "i2c1", 4000000, &ctlr[0], n900i2cinit, n900i2cio },- { "i2c2", 4000000, &ctlr[1], n900i2cinit, n900i2cio },- { "i2c3", 4000000, &ctlr[2], n900i2cinit, n900i2cio },- };
-
- for(i = 0; i < nelem(bus); i++)
- addi2cbus(&bus[i]);
-}
--- /dev/null
+++ b/sys/src/9/n900/i2comap.c
@@ -1,0 +1,217 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+#include "../port/error.h"
+#include "../port/i2c.h"
+
+enum {+ Rrev = 0x00,
+ Rie = 0x04,
+ Ris = 0x08,
+ Ial = 1 << 0,
+ Inack = 1 << 1,
+ Iardy = 1 << 2,
+ Irrdy = 1 << 3,
+ Ixrdy = 1 << 4,
+ Ibb = 1 << 12,
+ Iall = 0xffff,
+
+ Rwe = 0x0c,
+ Rsyss = 0x10,
+ SSreset = 1 << 0,
+
+ Rbuf = 0x14,
+ Rcnt = 0x18,
+ Rdata = 0x1c,
+ Rsysc = 0x20,
+ SCreset = 1 << 1,
+
+ Rcon = 0x24,
+ Cstt = 1 << 0,
+ Cstp = 1 << 1,
+ Cxoa3 = 1 << 4,
+ Cxoa2 = 1 << 5,
+ Cxoa1 = 1 << 6,
+ Cxoa0 = 1 << 7,
+ Cxa = 1 << 8,
+ Ctrx = 1 << 9,
+ Cmst = 1 << 10,
+ Cstb = 1 << 11,
+ Cen = 1 << 15,
+
+ Raddr = 0x2c,
+};
+
+#define csr32r(c, r) ((c)->io[(r)/4])
+#define csr32w(c, r, w) ((c)->io[(r)/4] = (w))
+
+typedef struct Ctlr Ctlr;
+struct Ctlr {+ u32int *io;
+ ulong irq;
+
+ Rendez;
+};
+
+static Ctlr ctlr[] = {+ { .io = (u32int*) PHYSI2C1, .irq = IRQI2C1 },+ { .io = (u32int*) PHYSI2C2, .irq = IRQI2C2 },+ { .io = (u32int*) PHYSI2C3, .irq = IRQI2C3 },+};
+
+static void
+omapi2cwaitbus(Ctlr *ctlr)
+{+ /* FIXME: timeout here? */
+ while(csr32r(ctlr, Ris) & Ibb)
+ ;
+}
+
+static int
+omapi2cwaitirq(void *arg)
+{+ Ctlr *ctlr = arg; return csr32r(ctlr, Ris);
+}
+
+static uint
+omapi2cwait(Ctlr *ctlr)
+{+ uint s;
+
+ /* FIXME: timeout here? */
+ while(!(s = csr32r(ctlr, Ris))) {+ if(!up || !islo())
+ continue;
+
+ tsleep(ctlr, omapi2cwaitirq, ctlr, 5);
+ }
+
+ return s;
+}
+
+static void
+omapi2cflush(Ctlr *ctlr)
+{+ while(csr32r(ctlr, Ris) & Irrdy) {+ USED(csr32r(ctlr, Rdata));
+ csr32w(ctlr, Ris, Irrdy);
+ }
+}
+
+static void
+omapi2cintr(Ureg *, void *arg)
+{+ Ctlr *ctlr;
+
+ ctlr = arg;
+ wakeup(ctlr);
+}
+
+static int
+omapi2cinit(I2Cbus *bus)
+{+ Ctlr *ctlr;
+
+ /* reset the ctlr */
+ ctlr = bus->ctlr;
+ csr32w(ctlr, Rsysc, SCreset);
+ csr32w(ctlr, Rcon, Cen);
+
+ /* FIXME: timeout here? */
+ while(!(csr32r(ctlr, Rsyss) & SSreset))
+ ;
+
+ intrenable(ctlr->irq, omapi2cintr, ctlr, 0, bus->name);
+ return 0;
+}
+
+static int
+omapi2cio(I2Cbus *bus, uchar *pkt, int olen, int ilen)
+{+ Ctlr *ctlr;
+ uint con, addr, stat;
+ uint o;
+
+ ctlr = bus->ctlr;
+ if(olen <= 0 || pkt == nil)
+ return -1;
+
+ o = 0;
+ con = Cen | Cmst | Ctrx | Cstp | Cstt;
+ if((pkt[o] & 0xf8) == 0xf0)
+ return -1;
+ addr = pkt[o++] >> 1;
+
+ /* wait for bus */
+ omapi2cwaitbus(ctlr);
+
+ /* first attempt to probe, will get nack here if no dev */
+ csr32w(ctlr, Rcnt, olen);
+ csr32w(ctlr, Raddr, addr);
+ csr32w(ctlr, Rcon, con);
+ stat = omapi2cwait(ctlr);
+ if(stat & Inack || stat & Ial) {+ o = -1; goto err;
+ }
+
+ /* transmit */
+ while(o < olen) {+ stat = omapi2cwait(ctlr);
+ if(stat == 0 || stat & Inack || stat & Ial) {+ o = -1; goto err;
+ }
+
+ if(stat & Iardy) {+ csr32w(ctlr, Ris, Iardy);
+ break;
+ }
+
+ if(stat & Ixrdy) {+ csr32w(ctlr, Rdata, pkt[o++]);
+ csr32w(ctlr, Ris, Ixrdy);
+ }
+ }
+
+ /* receive */
+ csr32w(ctlr, Rcnt, ilen);
+ csr32w(ctlr, Raddr, addr);
+ csr32w(ctlr, Rcon, Cen | Cmst | Cstp | Cstt);
+ while(o < olen + ilen) {+ stat = omapi2cwait(ctlr);
+ if(stat == 0 || stat & Inack || stat & Ial) {+ o = -1; goto err;
+ }
+
+ if(stat & Iardy) {+ csr32w(ctlr, Ris, Iardy);
+ break;
+ }
+
+ if(stat & Irrdy) {+ pkt[o++] = csr32r(ctlr, Rdata);
+ csr32w(ctlr, Ris, Irrdy);
+ }
+ }
+
+err:
+ omapi2cflush(ctlr);
+ csr32w(ctlr, Ris, Iall);
+ return o;
+}
+
+void
+i2comaplink(void)
+{+ int i;
+ static I2Cbus bus[] = {+ { "i2c1", 4000000, &ctlr[0], omapi2cinit, omapi2cio },+ { "i2c2", 4000000, &ctlr[1], omapi2cinit, omapi2cio },+ { "i2c3", 4000000, &ctlr[2], omapi2cinit, omapi2cio },+ };
+
+ for(i = 0; i < nelem(bus); i++)
+ addi2cbus(&bus[i]);
+}
--- a/sys/src/9/n900/mmcn900.c
+++ /dev/null
@@ -1,308 +1,0 @@
-#include "u.h"
-#include "../port/lib.h"
-#include "../port/error.h"
-#include "mem.h"
-#include "dat.h"
-#include "fns.h"
-#include "io.h"
-#include "../port/pci.h"
-#include "../port/sd.h"
-
-enum {- Rsysc = 0x10,
- SCreset = 1 << 1,
- Rsyss = 0x14,
- SSreset = 1 << 0,
- Rcsre = 0x24,
- Rcon = 0x28,
- Rpwcnt = 0x2c,
- Rblk = 0x104,
- Rarg = 0x108,
- Rcmd = 0x10c,
- CRnone = 0 << 16,
- CR136 = 1 << 16,
- CR48 = 2 << 16,
- CR48busy = 3 << 16,
- CRmask = 3 << 16,
-
- CFcheckidx = 1 << 19,
- CFcheckcrc = 1 << 20,
- CFdata = 1 << 21,
- CFdataread = 1 << 4,
- CFdatamulti = 1 << 5,
-
- CTnone = 0 << 22,
- CTbus = 1 << 22,
- CTfunc = 2 << 22,
- CTio = 3 << 22,
- Rrsp10 = 0x110,
- Rrsp32 = 0x114,
- Rrsp54 = 0x118,
- Rrsp76 = 0x11c,
- Rdata = 0x120,
- Rpstate = 0x124,
- Rhctl = 0x128,
- Rsysctl = 0x12c,
- Rstatus = 0x130,
- STcmd = 1 << 0,
- STtransfer = 1 << 1,
- STbufwrite = 1 << 4,
- STbufread = 1 << 5,
-
- STmaskok = 0xffff << 0,
- STmaskerr = 0xffff << 16,
- Rie = 0x134,
- Rise = 0x138,
- Rac12 = 0x13c,
- Rcapa = 0x140,
- Rcapacur = 0x148,
- Rrev = 0x1fc,
-};
-
-#define csr32r(c, r) ((c)->io[(r)/4])
-#define csr32w(c, r, w) ((c)->io[(r)/4] = (w))
-
-typedef struct Ctlr Ctlr;
-struct Ctlr {- char *name;
- u32int *io;
- ulong irq;
-
- struct {- uint bcount;
- uint bsize;
- } cmd;
-
- Lock;
- Rendez;
-};
-
-static int
-n900mmcinit(SDio *io)
-{- Ctlr *ctlr;
-
- ctlr = io->aux;
- csr32w(ctlr, Rsysc, SCreset);
- while(!(csr32r(ctlr, Rsyss) & SSreset))
- ;
-
- return 0;
-}
-
-static void
-n900mmcenable(SDio *)
-{-}
-
-static int
-n900mmcinquiry(SDio *, char *inquiry, int len)
-{- return snprint(inquiry, len, "MMC Host Controller");
-}
-
-static void
-n900mmcintr(Ureg *, void *aux)
-{- Ctlr *ctlr;
-
- ctlr = aux;
- ilock(ctlr);
- if(csr32r(ctlr, Rstatus) & STcmd)
- wakeup(ctlr);
-
- iunlock(ctlr);
-}
-
-static int
-n900mmcdone(void *aux)
-{- Ctlr *ctlr = aux;
-
- if(csr32r(ctlr, Rstatus) & STcmd)
- return 1;
-
- return 0;
-}
-
-static int
-n900mmccmd(SDio *io, SDiocmd *iocmd, u32int arg, u32int *resp)
-{- Ctlr *ctlr;
- u32int cmd;
-
- /* prepare flags for this command */
- ctlr = io->aux;
- cmd = iocmd->index << 24;
- switch(iocmd->resp) {- case 0: cmd |= CRnone; break;
- case 2: cmd |= CR136 | CFcheckcrc; break;
- case 3: cmd |= CR48; break;
- case 1:
- if(iocmd->busy) {- cmd |= CR48busy | CFcheckidx | CFcheckcrc;
- break;
- }
-
- default:
- cmd |= CR48 | CFcheckidx | CFcheckcrc;
- break;
- }
-
- /* if there is data, set the data, read, and multi flags */
- if(iocmd->data) {- cmd |= CFdata;
- if(iocmd->data & 1)
- cmd |= CFdataread;
- if(iocmd->data > 2)
- cmd |= CFdatamulti;
- }
-
- /* off it goes, wait for a response */
- csr32w(ctlr, Rstatus, ~0);
- csr32w(ctlr, Rarg, arg);
- csr32w(ctlr, Rcmd, cmd);
-
- /* wait for command to be done */
- tsleep(ctlr, n900mmcdone, ctlr, 100);
- if(csr32r(ctlr, Rstatus) & STmaskerr)
- error(Eio);
-
- /* unpack the response */
- switch(cmd & CRmask) {- case CRnone:
- resp[0] = 0;
- break;
-
- case CR136:
- resp[0] = csr32r(ctlr, Rrsp10);
- resp[1] = csr32r(ctlr, Rrsp32);
- resp[2] = csr32r(ctlr, Rrsp54);
- resp[3] = csr32r(ctlr, Rrsp76);
- break;
-
- case CR48:
- case CR48busy:
- resp[0] = csr32r(ctlr, Rrsp10);
- break;
- }
-
- return 0;
-}
-
-static void
-n900mmciosetup(SDio *io, int, void *, int bsize, int bcount)
-{- Ctlr *ctlr;
-
- ctlr = io->aux;
- if(bsize == 0 || (bsize & 3) != 0)
- error(Egreg);
-
- ctlr->cmd.bsize = bsize;
- ctlr->cmd.bcount = bcount;
- csr32w(ctlr, Rblk, (bsize & 0x3ff) | (bcount << 16));
-}
-
-static void
-n900mmcbufread(Ctlr *ctlr, uchar *buf, int len)
-{- for(len >>= 2; len > 0; len--) {- *((u32int*)buf) = csr32r(ctlr, Rdata);
- buf += 4;
- }
-}
-
-static void
-n900mmcbufwrite(Ctlr *ctlr, uchar *buf, int len)
-{- for(len >>= 2; len > 0; len--) {- csr32w(ctlr, Rdata, *((u32int*)buf));
- buf += 4;
- }
-}
-
-static void
-n900mmcio(SDio *io, int write, uchar *buf, int len)
-{- Ctlr *ctlr;
- u32int stat, n;
-
- ctlr = io->aux;
- if(len != ctlr->cmd.bsize * ctlr->cmd.bcount)
- error(Egreg);
-
- while(len > 0) {- stat = csr32r(ctlr, Rstatus);
- if(stat & STmaskerr) {- csr32w(ctlr, Rstatus, STmaskerr);
- error(Eio);
- }
-
- if(stat & STbufwrite) {- csr32w(ctlr, Rstatus, STbufwrite);
- if(!write)
- error(Eio);
-
- n = len;
- if(n > ctlr->cmd.bsize)
- n = ctlr->cmd.bsize;
-
- n900mmcbufwrite(ctlr, buf, n);
- len -= n;
- buf += n;
- }
-
- if(stat & STbufread) {- csr32w(ctlr, Rstatus, STbufread);
- if(write)
- error(Eio);
-
- n = len;
- if(n > ctlr->cmd.bsize)
- n = ctlr->cmd.bsize;
-
- n900mmcbufread(ctlr, buf, n);
- len -= n;
- buf += n;
- }
-
- if(stat & STtransfer) {- csr32w(ctlr, Rstatus, STtransfer);
- if(len != 0)
- error(Eio);
- }
- }
-}
-
-static void
-n900mmcbus(SDio *, int, int)
-{- /* FIXME: change bus width */
-}
-
-void
-mmcn900link(void)
-{- int i;
- static Ctlr ctlr[2] = {- { .name = "mmc1", .io = (u32int*) PHYSMMC1, .irq = IRQMMC1, },- { .name = "mmc2", .io = (u32int*) PHYSMMC2, .irq = IRQMMC2, },- };
-
- static SDio io[nelem(ctlr)];
- for(i = 0; i < nelem(io); i++) {- io[i].name = "mmc",
- io[i].init = n900mmcinit,
- io[i].enable = n900mmcenable,
- io[i].inquiry = n900mmcinquiry,
- io[i].cmd = n900mmccmd,
- io[i].iosetup = n900mmciosetup,
- io[i].io = n900mmcio,
- io[i].bus = n900mmcbus,
- io[i].aux = &ctlr[i];
-
- addmmcio(&io[i]);
- intrenable(ctlr[i].irq, n900mmcintr, &ctlr[i], BUSUNKNOWN, ctlr[i].name);
- }
-}
--- /dev/null
+++ b/sys/src/9/n900/mmcomap.c
@@ -1,0 +1,309 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "../port/error.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+#include "../port/pci.h"
+#include "../port/sd.h"
+
+enum {+ Rsysc = 0x10,
+ SCreset = 1 << 1,
+ Rsyss = 0x14,
+ SSreset = 1 << 0,
+ Rcsre = 0x24,
+ Rcon = 0x28,
+ Rpwcnt = 0x2c,
+ Rblk = 0x104,
+ Rarg = 0x108,
+ Rcmd = 0x10c,
+ CRnone = 0 << 16,
+ CR136 = 1 << 16,
+ CR48 = 2 << 16,
+ CR48busy = 3 << 16,
+ CRmask = 3 << 16,
+
+ CFcheckidx = 1 << 19,
+ CFcheckcrc = 1 << 20,
+ CFdata = 1 << 21,
+ CFdataread = 1 << 4,
+ CFdatamulti = 1 << 5,
+
+ CTnone = 0 << 22,
+ CTbus = 1 << 22,
+ CTfunc = 2 << 22,
+ CTio = 3 << 22,
+ Rrsp10 = 0x110,
+ Rrsp32 = 0x114,
+ Rrsp54 = 0x118,
+ Rrsp76 = 0x11c,
+ Rdata = 0x120,
+ Rpstate = 0x124,
+ Rhctl = 0x128,
+ Rsysctl = 0x12c,
+ Rstatus = 0x130,
+ STcmd = 1 << 0,
+ STtransfer = 1 << 1,
+ STbufwrite = 1 << 4,
+ STbufread = 1 << 5,
+
+ STmaskok = 0xffff << 0,
+ STmaskerr = 0xffff << 16,
+ Rie = 0x134,
+ Rise = 0x138,
+ Rac12 = 0x13c,
+ Rcapa = 0x140,
+ Rcapacur = 0x148,
+ Rrev = 0x1fc,
+};
+
+#define csr32r(c, r) ((c)->io[(r)/4])
+#define csr32w(c, r, w) ((c)->io[(r)/4] = (w))
+
+typedef struct Ctlr Ctlr;
+struct Ctlr {+ char *name;
+ u32int *io;
+ ulong irq;
+
+ struct {+ uint bcount;
+ uint bsize;
+ } cmd;
+
+ Lock;
+ Rendez;
+};
+
+static int
+omapmmcinit(SDio *io)
+{+ Ctlr *ctlr;
+
+ ctlr = io->aux;
+ csr32w(ctlr, Rsysc, SCreset);
+ while(!(csr32r(ctlr, Rsyss) & SSreset))
+ ;
+
+ return 0;
+}
+
+static void
+omapmmcenable(SDio *)
+{+}
+
+static int
+omapmmcinquiry(SDio *, char *inquiry, int len)
+{+ return snprint(inquiry, len, "MMC Host Controller");
+}
+
+static void
+omapmmcintr(Ureg *, void *aux)
+{+ Ctlr *ctlr;
+
+ ctlr = aux;
+ ilock(ctlr);
+ if(csr32r(ctlr, Rstatus) & STcmd)
+ wakeup(ctlr);
+
+ iunlock(ctlr);
+}
+
+static int
+omapmmcdone(void *aux)
+{+ Ctlr *ctlr = aux;
+
+ if(csr32r(ctlr, Rstatus) & STcmd)
+ return 1;
+
+ return 0;
+}
+
+static int
+omapmmccmd(SDio *io, SDiocmd *iocmd, u32int arg, u32int *resp)
+{+ Ctlr *ctlr;
+ u32int cmd;
+
+ /* prepare flags for this command */
+ ctlr = io->aux;
+ cmd = iocmd->index << 24;
+ switch(iocmd->resp) {+ case 0: cmd |= CRnone; break;
+ case 2: cmd |= CR136 | CFcheckcrc; break;
+ case 3: cmd |= CR48; break;
+ case 1:
+ if(iocmd->busy) {+ cmd |= CR48busy | CFcheckidx | CFcheckcrc;
+ break;
+ }
+
+ default:
+ cmd |= CR48 | CFcheckidx | CFcheckcrc;
+ break;
+ }
+
+ /* if there is data, set the data, read, and multi flags */
+ if(iocmd->data) {+ cmd |= CFdata;
+ if(iocmd->data & 1)
+ cmd |= CFdataread;
+ if(iocmd->data > 2)
+ cmd |= CFdatamulti;
+ }
+
+ /* off it goes, wait for a response */
+ csr32w(ctlr, Rstatus, ~0);
+ csr32w(ctlr, Rarg, arg);
+ csr32w(ctlr, Rcmd, cmd);
+
+ /* wait for command to be done */
+ tsleep(ctlr, omapmmcdone, ctlr, 100);
+ if(csr32r(ctlr, Rstatus) & STmaskerr)
+ error(Eio);
+
+ /* unpack the response */
+ switch(cmd & CRmask) {+ case CRnone:
+ resp[0] = 0;
+ break;
+
+ case CR136:
+ resp[0] = csr32r(ctlr, Rrsp10);
+ resp[1] = csr32r(ctlr, Rrsp32);
+ resp[2] = csr32r(ctlr, Rrsp54);
+ resp[3] = csr32r(ctlr, Rrsp76);
+ break;
+
+ case CR48:
+ case CR48busy:
+ resp[0] = csr32r(ctlr, Rrsp10);
+ break;
+ }
+
+ return 0;
+}
+
+static void
+omapmmciosetup(SDio *io, int, void *, int bsize, int bcount)
+{+ Ctlr *ctlr;
+
+ ctlr = io->aux;
+ if(bsize == 0 || (bsize & 3) != 0)
+ error(Egreg);
+
+ ctlr->cmd.bsize = bsize;
+ ctlr->cmd.bcount = bcount;
+ csr32w(ctlr, Rblk, (bsize & 0x3ff) | (bcount << 16));
+}
+
+static void
+omapmmcbufread(Ctlr *ctlr, uchar *buf, int len)
+{+ for(len >>= 2; len > 0; len--) {+ *((u32int*)buf) = csr32r(ctlr, Rdata);
+ buf += 4;
+ }
+}
+
+static void
+omapmmcbufwrite(Ctlr *ctlr, uchar *buf, int len)
+{+ for(len >>= 2; len > 0; len--) {+ csr32w(ctlr, Rdata, *((u32int*)buf));
+ buf += 4;
+ }
+}
+
+static void
+omapmmcio(SDio *io, int write, uchar *buf, int len)
+{+ Ctlr *ctlr;
+ u32int stat, n;
+
+ ctlr = io->aux;
+ if(len != ctlr->cmd.bsize * ctlr->cmd.bcount)
+ error(Egreg);
+
+ while(len > 0) {+ stat = csr32r(ctlr, Rstatus);
+ if(stat & STmaskerr) {+ csr32w(ctlr, Rstatus, STmaskerr);
+ error(Eio);
+ }
+
+ if(stat & STbufwrite) {+ csr32w(ctlr, Rstatus, STbufwrite);
+ if(!write)
+ error(Eio);
+
+ n = len;
+ if(n > ctlr->cmd.bsize)
+ n = ctlr->cmd.bsize;
+
+ omapmmcbufwrite(ctlr, buf, n);
+ len -= n;
+ buf += n;
+ }
+
+ if(stat & STbufread) {+ csr32w(ctlr, Rstatus, STbufread);
+ if(write)
+ error(Eio);
+
+ n = len;
+ if(n > ctlr->cmd.bsize)
+ n = ctlr->cmd.bsize;
+
+ omapmmcbufread(ctlr, buf, n);
+ len -= n;
+ buf += n;
+ }
+
+ if(stat & STtransfer) {+ csr32w(ctlr, Rstatus, STtransfer);
+ if(len != 0)
+ error(Eio);
+ }
+ }
+}
+
+static void
+omapmmcbus(SDio *, int, int)
+{+ /* FIXME: change bus width */
+}
+
+void
+mmcomaplink(void)
+{+ int i;
+ static Ctlr ctlr[] = {+ { .name = "mmc 1", .io = (u32int*) PHYSMMC1, .irq = IRQMMC1, },+ { .name = "mmc 2", .io = (u32int*) PHYSMMC2, .irq = IRQMMC2, },+ { .name = "mmc 3", .io = (u32int*) PHYSMMC3, .irq = IRQMMC3, },+ };
+
+ static SDio io[nelem(ctlr)];
+ for(i = 0; i < nelem(io); i++) {+ io[i].name = "mmc",
+ io[i].init = omapmmcinit,
+ io[i].enable = omapmmcenable,
+ io[i].inquiry = omapmmcinquiry,
+ io[i].cmd = omapmmccmd,
+ io[i].iosetup = omapmmciosetup,
+ io[i].io = omapmmcio,
+ io[i].bus = omapmmcbus,
+ io[i].aux = &ctlr[i];
+
+ addmmcio(&io[i]);
+ intrenable(ctlr[i].irq, omapmmcintr, &ctlr[i], BUSUNKNOWN, ctlr[i].name);
+ }
+}
--- a/sys/src/9/n900/n900
+++ b/sys/src/9/n900/n900
@@ -17,8 +17,8 @@
draw screen
- kbd devi2c
- rtc devi2c
+ kbdtwl devi2c
+ rtctwl devi2c
uart
usb
@@ -25,9 +25,9 @@
i2c
misc
- uartn900
+ uartomap
- sdmmc mmcn900
+ sdmmc mmcomap
sdloop
sdram
@@ -36,8 +36,8 @@
dtracydev
link
- i2cn900 devi2c
- mmcn900
+ i2comap devi2c
+ mmcomap
port
int cpuserver = 0;
--- a/sys/src/9/n900/uartn900.c
+++ /dev/null
@@ -1,268 +1,0 @@
-#include "u.h"
-#include "../port/lib.h"
-#include "mem.h"
-#include "dat.h"
-#include "fns.h"
-#include "io.h"
-#include "../port/error.h"
-
-enum {- Rdll = 0x00,
- Rrhr = 0x00,
- Rthr = 0x00,
- Rdlh = 0x04,
- Rier = 0x04,
- IErhr = 1 << 0,
- IEthr = 1 << 1,
- IEls = 1 << 2,
- IEms = 1 << 3,
- Riir = 0x08,
- Ipending = 1 << 0,
- Imodem = 0x00,
- Ithr = 0x01,
- Irhr = 0x02,
- Ils = 0x03,
- Irxt = 0x06,
- Ixoff = 0x08,
- Icts = 0x10,
- Imask = 0x1f,
- Rfcr = 0x08,
- FCRen = 1 << 0,
- Refr = 0x08,
- Rlcr = 0x0c,
- Rmcr = 0x10,
- Rxon1 = 0x10,
- Rlsr = 0x14,
- LSRrxempty = 1 << 0,
- LSRrxover = 1 << 1,
- LSRrxparity = 1 << 2,
- LSRrxframe = 1 << 3,
- LSRrxbreak = 1 << 4,
- LSRtxempty = 1 << 5,
- LSRtxshift = 1 << 6,
- LSRrxstat = 1 << 7,
- Rxon2 = 0x14,
- Rmsr = 0x18,
- Rtcr = 0x18,
- Rxoff1 = 0x18,
- Rspr = 0x1c,
- Rtlr = 0x1c,
- Rxoff2 = 0x1c,
- Rmdr1 = 0x20,
- Rmdr2 = 0x24,
- Rsysc = 0x54,
- SCreset = 1 << 1,
- Rsyss = 0x58,
- SSreset = 1 << 0,
-};
-
-#define csr32r(c, r) ((c)->io[(r)/4])
-#define csr32w(c, r, w) ((c)->io[(r)/4] = (w))
-
-typedef struct Ctlr Ctlr;
-struct Ctlr {- Lock;
-
- u32int *io;
- ulong irq;
-
- int ie;
-};
-
-extern PhysUart n900physuart;
-
-static Ctlr ctlr[] = {- { .io = (u32int*) PHYSUART1, .irq = IRQUART1, },- { .io = (u32int*) PHYSUART2, .irq = IRQUART2, },- { .io = (u32int*) PHYSUART3, .irq = IRQUART3, },-};
-
-static Uart n900uart[] = {- {- .regs = &ctlr[0],
- .name = "uart1",
- .freq = 48000000,
- .phys = &n900physuart,
- .next = &n900uart[1],
- },
- {- .regs = &ctlr[1],
- .name = "uart2",
- .freq = 48000000,
- .phys = &n900physuart,
- .next = &n900uart[2],
- },
- {- .regs = &ctlr[2],
- .name = "uart3",
- .freq = 48000000,
- .phys = &n900physuart,
- .next = nil,
- },
-};
-
-static Uart *
-n900uartpnp(void)
-{- return n900uart;
-}
-
-static long
-n900uartstatus(Uart *, void *, long, long)
-{- return 0;
-}
-
-static void
-n900uartintr(Ureg *, void *arg)
-{- Uart *uart;
- Ctlr *ctlr;
- int lsr;
- char c;
-
- uart = arg;
- ctlr = uart->regs;
-
- ilock(ctlr);
- switch((csr32r(ctlr, Riir) >> 1) & Imask) {- case Ithr:
- uartkick(uart);
- break;
-
- case Irhr:
- while((lsr = csr32r(ctlr, Rlsr)) & LSRrxempty) {- c = csr32r(ctlr, Rrhr);
-
- if(lsr & LSRrxover) { uart->oerr++; break; }- if(lsr & LSRrxparity) { uart->perr++; break; }- if(lsr & LSRrxframe) { uart->ferr++; break; }-
- uartrecv(uart, c);
- }
-
- break;
- }
-
- iunlock(ctlr);
-}
-
-static void
-n900uartenable(Uart *uart, int ie)
-{- Ctlr *ctlr;
-
- ctlr = uart->regs;
- ilock(ctlr);
-
- csr32w(ctlr, Rsysc, SCreset);
- while(!(csr32r(ctlr, Rsyss) & SSreset))
- ;
-
- csr32w(ctlr, Rfcr, FCRen);
- if(ie) {- if(!ctlr->ie) {- intrenable(ctlr->irq, n900uartintr, uart, 0, uart->name);
- ctlr->ie = 1;
- }
-
- csr32w(ctlr, Rier, IErhr);
- }
-
- iunlock(ctlr);
-}
-
-static void
-n900uartdisable(Uart *uart)
-{- Ctlr *ctlr;
-
- ctlr = uart->regs;
-
- ilock(ctlr);
- csr32w(ctlr, Rier, 0);
- if(ctlr->ie) {- intrdisable(ctlr->irq, n900uartintr, uart, 0, uart->name);
- ctlr->ie = 0;
- }
-
- iunlock(ctlr);
-}
-
-static void
-n900uartkick(Uart *uart)
-{- Ctlr *ctlr;
- int i;
-
- ctlr = uart->regs;
- if(uart->blocked)
- return;
-
- for(i = 0; i < 128; i++) {- if(csr32r(ctlr, Rlsr) & LSRtxempty) {- if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
- break;
-
- csr32w(ctlr, Rthr, *uart->op++);
- }
- }
-}
-
-static int
-n900uartgetc(Uart *uart)
-{- Ctlr *ctlr;
-
- ctlr = uart->regs;
- while(!(csr32r(ctlr, Rlsr) & LSRrxempty))
- ;
-
- return csr32r(ctlr, Rrhr);
-}
-
-static void
-n900uartputc(Uart *uart, int c)
-{- Ctlr *ctlr;
-
- ctlr = uart->regs;
- while(!(csr32r(ctlr, Rlsr) & LSRtxempty))
- ;
-
- csr32w(ctlr, Rthr, c);
-}
-
-static void n900uartnop(Uart *, int) {}-static int n900uartnope(Uart *, int) { return -1; }-
-PhysUart n900physuart = {- .name = "n900",
-
- .pnp = n900uartpnp,
- .enable = n900uartenable,
- .disable = n900uartdisable,
- .kick = n900uartkick,
- .status = n900uartstatus,
- .getc = n900uartgetc,
- .putc = n900uartputc,
-
- .dobreak = n900uartnop,
- .baud = n900uartnope,
- .bits = n900uartnope,
- .stop = n900uartnope,
- .parity = n900uartnope,
- .modemctl = n900uartnop,
- .rts = n900uartnop,
- .dtr = n900uartnop,
- .fifo = n900uartnop,
- .power = n900uartnop,
-};
-
-void
-uartinit(void)
-{- consuart = &n900uart[2];
- consuart->console = 1;
- uartputs(kmesg.buf, kmesg.n);
-}
--- /dev/null
+++ b/sys/src/9/n900/uartomap.c
@@ -1,0 +1,268 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "io.h"
+#include "../port/error.h"
+
+enum {+ Rdll = 0x00,
+ Rrhr = 0x00,
+ Rthr = 0x00,
+ Rdlh = 0x04,
+ Rier = 0x04,
+ IErhr = 1 << 0,
+ IEthr = 1 << 1,
+ IEls = 1 << 2,
+ IEms = 1 << 3,
+ Riir = 0x08,
+ Ipending = 1 << 0,
+ Imodem = 0x00,
+ Ithr = 0x01,
+ Irhr = 0x02,
+ Ils = 0x03,
+ Irxt = 0x06,
+ Ixoff = 0x08,
+ Icts = 0x10,
+ Imask = 0x1f,
+ Rfcr = 0x08,
+ FCRen = 1 << 0,
+ Refr = 0x08,
+ Rlcr = 0x0c,
+ Rmcr = 0x10,
+ Rxon1 = 0x10,
+ Rlsr = 0x14,
+ LSRrxempty = 1 << 0,
+ LSRrxover = 1 << 1,
+ LSRrxparity = 1 << 2,
+ LSRrxframe = 1 << 3,
+ LSRrxbreak = 1 << 4,
+ LSRtxempty = 1 << 5,
+ LSRtxshift = 1 << 6,
+ LSRrxstat = 1 << 7,
+ Rxon2 = 0x14,
+ Rmsr = 0x18,
+ Rtcr = 0x18,
+ Rxoff1 = 0x18,
+ Rspr = 0x1c,
+ Rtlr = 0x1c,
+ Rxoff2 = 0x1c,
+ Rmdr1 = 0x20,
+ Rmdr2 = 0x24,
+ Rsysc = 0x54,
+ SCreset = 1 << 1,
+ Rsyss = 0x58,
+ SSreset = 1 << 0,
+};
+
+#define csr32r(c, r) ((c)->io[(r)/4])
+#define csr32w(c, r, w) ((c)->io[(r)/4] = (w))
+
+typedef struct Ctlr Ctlr;
+struct Ctlr {+ Lock;
+
+ u32int *io;
+ ulong irq;
+
+ int ie;
+};
+
+extern PhysUart omapphysuart;
+
+static Ctlr ctlr[] = {+ { .io = (u32int*) PHYSUART1, .irq = IRQUART1, },+ { .io = (u32int*) PHYSUART2, .irq = IRQUART2, },+ { .io = (u32int*) PHYSUART3, .irq = IRQUART3, },+};
+
+static Uart omapuart[] = {+ {+ .regs = &ctlr[0],
+ .name = "uart1",
+ .freq = 48000000,
+ .phys = &omapphysuart,
+ .next = &omapuart[1],
+ },
+ {+ .regs = &ctlr[1],
+ .name = "uart2",
+ .freq = 48000000,
+ .phys = &omapphysuart,
+ .next = &omapuart[2],
+ },
+ {+ .regs = &ctlr[2],
+ .name = "uart3",
+ .freq = 48000000,
+ .phys = &omapphysuart,
+ .next = nil,
+ },
+};
+
+static Uart *
+omapuartpnp(void)
+{+ return omapuart;
+}
+
+static long
+omapuartstatus(Uart *, void *, long, long)
+{+ return 0;
+}
+
+static void
+omapuartintr(Ureg *, void *arg)
+{+ Uart *uart;
+ Ctlr *ctlr;
+ int lsr;
+ char c;
+
+ uart = arg;
+ ctlr = uart->regs;
+
+ ilock(ctlr);
+ switch((csr32r(ctlr, Riir) >> 1) & Imask) {+ case Ithr:
+ uartkick(uart);
+ break;
+
+ case Irhr:
+ while((lsr = csr32r(ctlr, Rlsr)) & LSRrxempty) {+ c = csr32r(ctlr, Rrhr);
+
+ if(lsr & LSRrxover) { uart->oerr++; break; }+ if(lsr & LSRrxparity) { uart->perr++; break; }+ if(lsr & LSRrxframe) { uart->ferr++; break; }+
+ uartrecv(uart, c);
+ }
+
+ break;
+ }
+
+ iunlock(ctlr);
+}
+
+static void
+omapuartenable(Uart *uart, int ie)
+{+ Ctlr *ctlr;
+
+ ctlr = uart->regs;
+ ilock(ctlr);
+
+ csr32w(ctlr, Rsysc, SCreset);
+ while(!(csr32r(ctlr, Rsyss) & SSreset))
+ ;
+
+ csr32w(ctlr, Rfcr, FCRen);
+ if(ie) {+ if(!ctlr->ie) {+ intrenable(ctlr->irq, omapuartintr, uart, 0, uart->name);
+ ctlr->ie = 1;
+ }
+
+ csr32w(ctlr, Rier, IErhr);
+ }
+
+ iunlock(ctlr);
+}
+
+static void
+omapuartdisable(Uart *uart)
+{+ Ctlr *ctlr;
+
+ ctlr = uart->regs;
+
+ ilock(ctlr);
+ csr32w(ctlr, Rier, 0);
+ if(ctlr->ie) {+ intrdisable(ctlr->irq, omapuartintr, uart, 0, uart->name);
+ ctlr->ie = 0;
+ }
+
+ iunlock(ctlr);
+}
+
+static void
+omapuartkick(Uart *uart)
+{+ Ctlr *ctlr;
+ int i;
+
+ ctlr = uart->regs;
+ if(uart->blocked)
+ return;
+
+ for(i = 0; i < 128; i++) {+ if(csr32r(ctlr, Rlsr) & LSRtxempty) {+ if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
+ break;
+
+ csr32w(ctlr, Rthr, *uart->op++);
+ }
+ }
+}
+
+static int
+omapuartgetc(Uart *uart)
+{+ Ctlr *ctlr;
+
+ ctlr = uart->regs;
+ while(!(csr32r(ctlr, Rlsr) & LSRrxempty))
+ ;
+
+ return csr32r(ctlr, Rrhr);
+}
+
+static void
+omapuartputc(Uart *uart, int c)
+{+ Ctlr *ctlr;
+
+ ctlr = uart->regs;
+ while(!(csr32r(ctlr, Rlsr) & LSRtxempty))
+ ;
+
+ csr32w(ctlr, Rthr, c);
+}
+
+static void omapuartnop(Uart *, int) {}+static int omapuartnope(Uart *, int) { return -1; }+
+PhysUart omapphysuart = {+ .name = "omap",
+
+ .pnp = omapuartpnp,
+ .enable = omapuartenable,
+ .disable = omapuartdisable,
+ .kick = omapuartkick,
+ .status = omapuartstatus,
+ .getc = omapuartgetc,
+ .putc = omapuartputc,
+
+ .dobreak = omapuartnop,
+ .baud = omapuartnope,
+ .bits = omapuartnope,
+ .stop = omapuartnope,
+ .parity = omapuartnope,
+ .modemctl = omapuartnop,
+ .rts = omapuartnop,
+ .dtr = omapuartnop,
+ .fifo = omapuartnop,
+ .power = omapuartnop,
+};
+
+void
+uartinit(void)
+{+ consuart = &omapuart[2];
+ consuart->console = 1;
+ uartputs(kmesg.buf, kmesg.n);
+}